The present invention relates, in general, to the field of integrated circuit ("IC") memory devices. More particularly, the present invention relates to a self-timed data amplifier and method of especial utility with respect to dynamic random access memory ("DRAM") memory devices.
DRAM memory devices incorporate one or more arrays of memory cells, each consisting of a single transistor and associated capacitor. The transistor has one terminal coupled to an associated bit line and its gate coupled to a word line. Another terminal is generally coupled to circuit ground through the capacitor and by enabling the transistor via the word line, the charge on the capacitor may be placed on the associated bit line. Due to the dynamic nature of the charge stored in the capacitor, it must be periodically refreshed to replenish the leaked charge.
The changes in the bit line potential due to the charge in the capacitor are first amplified by a sense amplifier to be read as either a logic level "one" or "zero" depending on the charge which has been transferred to the bit lines. Generally the sense amplifiers compare the data from the memory cells with a reference level which is stored in corresponding reference cells. At this point, the data which has been read out is then re-written to the memory cells during a precharge operation and the data is passed by means of an internal input/output ("I/O") bus and a data amplifier to circuitry external to the memory device.
Currently, DRAM memory devices utilize static data amplifiers to drive the device data output. While generally sufficient for this purpose, they consume a relatively large amount of on-chip power resources. Moreover, conventional data amplifier technology incorporates clocked output paths which present some inherent risks in providing accurate data output if run at high speeds. Alternatively, if sufficient design margin is included in their operational speed, they can run too slowly and present an I/O bottleneck.